Read/write memories, also referred to as Random Access Memories (RAM) are widely used to store programs and data for microprocessors and other electronic devices. The availability of high speed, high density and low power RAM devices has played a crucial role in the price reduction of personal computers and in the integration of computer technology into consumer electronic devices.
A typical RAM includes a large number of memory cells arranged in an array of rows and columns. Each memory cell is typically capable of storing therein a binary digit, i.e. a binary ONE or a binary ZERO. Each row of the memory cell array is typically connected to a word line and each column of the memory cell array is typically connected to a pair of bit lines. Read and write operations are performed on an individual cell in the memory by addressing the appropriate row of the array using the word lines and addressing the appropriate cell in the addressed row using the bit lines. Depending upon the signals applied to the bit lines, a write operation may be performed for storing binary data in the RAM or a read operation may be performed for accessing binary data which is stored in the RAM. When read and write operations are not being performed, the RAM is typically placed in an idle operation for maintaining the binary data stored therein.
RAMs are typically divided into two general classes, depending upon the need to refresh the data stored in the RAM during the idle state. In particular, in a Dynamic Random Access Memory (DRAM), the data stored in the memory is lost unless the memory is periodically refreshed during the idle operation. In contrast, in a Static Random Access Memory (SRAM) there is no need to refresh the data during an idle operation, because the data stored therein is maintained as long as electrical power is supplied to the SRAM. In the present state of the art, it is generally possible to fabricate higher density DRAM arrays than SRAM arrays because the individual memory cells of a DRAM include fewer transistors than the individual cells of an SRAM. However, SRAMs tend to operate at higher speeds than DRAMs, because there is no need to refresh the data stored therein. Accordingly, both SRAMs and DRAMs are typically used in computer systems, with the SRAMs being used for high speed memory (often referred to as "cache" memory), while the DRAM is typically used for lower speed, lower cost mass memory.
Three general design criteria govern the performance of random access memories. They are density, speed and power dissipation. Density describes the number of memory cells that can be formed on a given integrated circuit chip. In general, as more cells are fabricated on a Very Large Scale Integration (VLSI) chip, cost is reduced and speed is increased.
The performance of random access memories is also limited by the power consumption thereof. As power consumption increases, more sophisticated packaging is necessary to allow the integrated circuit to dissipate the high power. Moreover, high power circuits require expensive power supplies, and limit applicability to portable or battery powered devices.
Finally, speed is also an important consideration in the operation of a random access memory because the time it takes to reliably access data from the memory and write data into the memory is an important parameter in the overall system speed. It will be understood by those having skill in the art that the parameters of speed, density and power dissipation are generally interrelated, with improvements in one area generally requiring tradeoffs in one or more of the other areas.
A typical SRAM cell is a six transistor cell. Four of the transistors form a pair of complementary inverters each of which includes an input and an output, with the input of the first complementary inverter being connected to the output of the second complementary inverter and the input of the second complementary inverter being connected to the output of the first complementary inverter. The pair of cross coupled inverters forms a latch for storing a binary digit therein as long as power is applied to the latch. The fifth and sixth transistors are a pair of "pass transistors" which provide external access to the memory cell for reading and writing operations. Typically, the controlled electrodes, (for example the source and drain electrodes) of the first pass transistor are serially connected between one of the associated bit lines and the output of the first complementary inverter, and the controlled electrodes of the second pass transistor are connected between the other associated bit line and the output of the second complementary inverter. The controlling electrodes (for example gate electrodes) of both pass transistors are connected to the associated word line. Thus, the pass transistors of all SRAM cells in a row of the array are connected to the associated word line, and the pass transistors of all SRAM cells in a column of the array are connected to the associated pair of bit lines.
In operation, when a word line is selected, one of the pass transistors in each of the cells in the selected row sink current from the associated bit line. The pass transistor in the cell which sinks the current will be dependent on the digital state of the RAM cell, but one pass transistor in each cell will sink current. After the word line is deselected, all of the bit lines are recharged up to a reference voltage, typically the power supply voltage V.sub.DD.
Unfortunately, the above described current sinking and bit line recharging in each cell connected to a selected word line consumes an excessive amount of power during read and write operations. For example, assume there are 256 columns in an SRAM array, so 256 pass transistor pairs are connected to each row. If the sink current for each pass transistor pair is 1 mA, then 256 mA is drawn upon selection of a word line and another 256 mA is drawn upon deselection of the word line. Although this power drain is a transitory power drain, which only occurs during selection and deselection of a word line, it nonetheless effects the transient power consumption of the SRAM.
Attempts have been made to decrease the transient power consumed during a word select/deselect operation by dividing the SRAM array into a plurality of smaller arrays, thus reducing the number of pass transistor pairs connected to any single word line. Unfortunately, word decoding time increases when the array is divided. The physical size of the array also increases, resulting in a decrease in density. Additional address line capacitance is also introduced, thereby increasing the power dissipation to the array, and a corresponding loss in speed.